Comparison circuits



Jan. 22, 1963 A. c. REYNOLDS, JR 3,075,176

COMPARISON cxcurrs Original Filed Feb. 26, 1957 18 sheetsheet 1 F/G.FIG? Has FIG. 4

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Jan. 22, 1963 A. c. REYNOLDS, JR 3,075,176

COMPARISON CIRCUITS Original Filed Feb. 26, 1957 18 Sheets-Sheet 2 Jan.22, 1963 18 Sheets-Sheet 3 Original Filed Feb. 26, 1957 AAA T tEz.

lNl/EN TOR 4. C. REYNOLDS JP. 81/

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Jan. 22, 1963 A. c. REYNOLDS, JR 3,075,176

COMPARISON CIRCUITS Original Filed Feb. 26, 1957 FIG 7 l8 Sheets-Sheet 5OJI INV

CORRECTION COMPLETED ERRR CHECK TIME READ PULSE Y lNl/EN TOP A. C.REYNOLDS JR W AT TOPNE V Jan. 22, 1963 A. c. REYNOLDS, JR 3,075,176

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COMPARISON CIRCUITS Original Filed Feb. 26, 1957 18 Sheets-Sheet 10 //vl EN TOP A. C. REYNOL 05 JR.

ATTORNEY FIG. 24

Jan. 22, 1963 Original Filed Feb. 26, 1957 FIG26 FIG.27

A. c. REYNOLDS, JR 3,075,176

COMPARISON CIRCUITS 18 Sheets-Sheet 11 FIG. 28

//v VENTGR ,4. C. REVNOI. 05 JR.

A TTORNE V 1963 A. c. REYNOLDS, JR 3,07

COMPARISON CIRCUITS Original Filed Feb; 26, 1957 18 Sheets-Sheet 12COUNTER SELECTION Y PULSES BIT - FROM E RING CCT- 77 F F|G.33

INVENTOR A. C. REYNOLDS JR.

BY 4 m 1963 A. c. REYNOLDS, JR 3,075,

COMPARISON CIRCUITS Original Filed Feb. 26, 1957 18 Sheets-Sheet 13 FIG.27

OUTPUT BITS EXTENTED TO FIGS! INVENTOR A. C. REYNOLDS JR.

ATTORNEY Jan. 22, 1963 A. c. REYNOLDS, JR 3,075,176

COMPARISON CIRCUITS Original Filed Feb. 26, 1957 18 Sheets-Sheet 14F/G.29

IN [/5 N TOR A. C. REVNOL 05 JR BV I ATTOPNEV Jan. 22, 1963 A. c.REYNOLDS, JR 3,

COMPARISON CIRCUITS Original Filed Feb. 26, 1957 18 Sheets-Sheet 15 NTORA. C. NOLllS JR.

COUNTER EM, I

CHECK TIME 18 Sheets-Sheet 16 A. C. REYNOLDS, JR

COMPARISON CIRCUITS FIG. 32

I I F INVENTOR ,4. C. REYNOLDS JR.

' ATTORNEY M q Ln R R .w/ l n q 345 W 3 8 ,9w QWk Jan. 22, 1963 OriginalFiled Feb. 26, 1957 COU/NTER CORRECT ION GATES 1963 A. c. REYNOLDS, JR3,075,

COMPARISON CIRCUITS Original Filed Feb. 26, 1957 18 Sheets-Sheet 17 A7'7'ORNEY United States Patent ()fiice 3,075,1'26 Patented Jan. 22, 1%63This is a division of application, Serial Number 642,509, now Patent No.2,969,912, filed February 26, 1957, for improvements in Error Detectingand Correcting Circuits.

This invention relates to means for detecting and correcting errors intransmitted information and particularly relates to means for comparingcoded information found at one point in an extensive electronic networkwith what should be identical coded information found elsewhere.

An object of the invention is to provide supervisory means for examiningcoded items of information, each accompanied by its unique checkingitems, and to delay the further processing movement thereof until adetected error can be corrected or until an alarm may be given throughdisabling means provided to report a non-correctable error.

The invention consists in general of a means for handling information intransit. Each item of information, which, by way of example, may be aten digit number before entry into a processing machine, has certaincheck digits derived therefrom and these check digits are thereafterassociated with this ten digit number and become part of the word. Onegroup of these check digits consists of the decimal equivalent of thebinary number formed by the selection of one of two distinguishablecharacteristics from each of the binary code representations of each ofthe decimal digits of the said ten digit number.

For purposes of explanation an example will be discussed in great detailthroughout this specification. It will be assumed that the decimalnumber the least significant position bit of each group, thus producingthe binary number which, translated into its decimal equivalent, becomesand which, expressed in the binary decimal notation (for purposes whichwill appear hereinafter), becomes Another unique check digit is derivedby using the units digit of the sum of the digits of the said number,this being known as the sum modulo 10 of the number. The

so that the digit 4 is a derived check digit which along with the number0754 is associated with the said number and which accompanies the saidnumber in its movements through the processing machine. This item ofinformation is precalculated so that when the number and its checkdigits are moved about they appear as and this is expressed in thebinary decimal code so that it forms a succession of fifteen four placecodes which may be transmitted over a conventional four Wire bit trunk.It will be assumed that the means for successively entering andtransmitting each of these codes over such a four wire bit trunk inwhich the bits are simultaneously moved is entirely conventional.

The invention consists of means for successively gating these fifteendigits into fifteen digit stores for processing which comprises twoprincipal operations. First the four check digits 0754 are translatedinto an equivalent binary number and this is compared with the ten digitnumber which has actually been stored. Let us assume that in processingand by reason of some random error, the second digit 6 has become a 7.The comparison would then be between and it will at once be apparentthat there is an error in the second place.

At the same time and during the entry of the ten digits of this word,these ten digits are summed step by step and the sum of the digits ofthe number containing the error comes out to be 45 so that the summodulo 10, which is 5, fails to compare with the last (fifteenth place)check digit 4.

These two check failures then immediately start a correcting operation.This consists of opening a gate to the second place digit store and theintroduction thereinto of a train of correcting pulses andsimultaneously therewith the introduction into the means for summing thedigits of exactly the same number of pulses. This has the effect ofadvancing the record in the second place digit store successivelythrough the values 8, 9', 0, 1, 2, 3, 4, 5 and 6 and simultaneouslytherewith of advancing the record in the summing device successivelythrough the values of 46, 47, 48, 49, 50, 51, 5'2, 53 and 54. When thelast value 54 is reached, its units value 4 will compare exactly withthe last place check digit and this will bring about a circuit changeconstituting a satisfaction signal which will stop further correctionoperations and will cause the corrected ten digit number to betransferred to a use circuit, such as an arithmetic section of acomputer.

It should be noted that if no error had been detected the said ten digititem of information would have been immediately passed along to the saiduse circuit.

From the above discussion, and further by way of example, it will appearthat with circuits and apparatus hereinabove set forth, an error can bedetected only if it appears in the 1 bit place of some one of the digitsforming the ten digit Word, for otherwise the four digit check 0754would remain the same while only the sum modulo 10 check digit wouldchange. Since under these conditions there would be an absence ofinformation necessary for the operation of the proper gate to the storecontaining the digit in error, this will be known as a non-correctableerror and can only result in an alarm.

It may also be noted that where the four digit check number shows adeviation but the sum modulo 10 check digit shows no deviation, thisalso constitutes a noncorrectable error for no information exists whichwill control the number of correction pulses which must be introducedinto the store or stores containing an erroneous number. Where more thanone erroneous decimal digit exists in store then a non-correctable errorwill be reported, for while the four digit check may lead to thediscovery of the location of such multiple errors, the single digit summodulo 10 check digit cannot report the differing magnitude of two ormore errors.

While the system outlined above is particularly useful for the detectionand correction of errors occurring in the transmission of data in pulseform, e.g. transmission of a number of pulses in seriatlm correspondingto the value of a digit as in the telephone dial system, it is to beunderstood that the present invention contemplates means for detectingand correcting errors occurring in single-error. The system outlinedabove is quite-accurate for data-transmitted in pulse form. This data,of course, may be subsequently translated'into the binary coded decimalform or into any other coded form. If, however, the transmission is overfour parallel wires in the binary coded decimal form, for example, thenthe check digits would be derived from parity or redundant bitsgenerated in any manner well known in the art. Thus, the even paritycheck bit for the digit 7' might be formed as follows. In the binarycoded decimal form, the digit 7 is represented as 0111 and the sum ofthe bits is 3, or odd, and thus a 1 is the even parity check bit. Thatis, 1 must be added to 3 to make the sum even. The binary check numberderived from the example 7 V in this manner would thus be which binarynumber translates into the decimal number This number with the modulo.10 sum of the digits, 4, is

now used in the same manner as explained above, and is transmitted as Itis to be noted that, in both the above examples,

two mutually exclusive characteristics of each digit have been chosen asthe basis for forming the binary check number, in the first case the oddor even characteristic of the decimal number and in the second case theodd or even characteristic of the sum of the bits used in the binarycoded form of such decimal number. The binary check number so formed hasbeen translated into the decimal system of notation for transmissionwith the information carrying digits. It is to be noted further that theinvention is not limited to the decimal system of notation since thebinary check number can be translated into any system of notation asdesired, for example,

base 36 or larger for handling both alphabetic and' numeric data.

It is further to be noted that in the first example given a singlerandom error in the 1 bit place may be specifically detected andcorrected when the odd or even value of a decimal digit is thecharacteristic used as a control. Experience with the transmission ofinformation particularly in great digital information handling networkssuch as the telephone system and the digital computers has shown thatthe occurrence of such single random errors is extremely rare and thatthe occurrence of a double error is so extraordinarily rare thatprovision for its detection is almost never made. However, the detectionand correction of an error in the 1 bit place alone will detect only 25%of the random errors for which it is believed provision should be madefor it is just as likely that a random error may occur in the 2 bit, the4 bit, or the 8 bit place as it is that such an error may occur in the 1bit place.

A feature of the invention therefore is a means for detecting andcorrecting a single error which may occur at random in any one of thefour places of the binarydecimal code. Consider the digit 6 which isexpressed in the binary-decimal code as 0110. The sum of the bits iseven and a random error in any one of these four places will change thesum to odd. If, by way of example, through a random error this code istransmitted as 0010, an error in the 4 bit place, the change from odd toeven would change the synthesized binary number from 1 Although thislast number translates to the decimal number 0796, this translation isimmaterial since it is the comparison of these two ten place binarynumbers whichris used to locate the error and since in the comparisoncircuits inequality appears in the second place (the 256 bit place) itis this digit as recorded at the distant end that must be corrected.

From a practical standpoint the code'0010 is equivalent to the decimalvalue 2. This changes the sum of the bits from even to odd and pointsout the location of an error asbeing in the second digital place. Thiswill require the transmission of 4 correcting pulses to advance theregister from 0010 through the value 0011 to the correct value 0110. Theerroneous code 0010 which is transmitted being equal to the decimalvalue 2, will cause the sum of the decimal digits to be 40 instead or":the proper sum 44, so that as the 4 correcting pulses are transmitted tothe second place register, they also advance the modulo 10 summingdevice from the value 40 through the value 41 to the value 44, whichgives the sum modulo 10 value of 4 and which compares exactly with themagnitude digit 4.

However, if through random error the code 0110 is sent as 0100', thevalue of the sum of the bits is changed from even to odd and thecorrection will take place by the transmission of 2 correcting pulses toadvance the second place register from the value 0100 successivelythrough the value OlOltoOllO. Since-the-code represents the decimalvalue 4, the sum of the digits calculated on the receipt of these codeswill turnout to be 42 showing the sum modulo ten equal to 2 and sincethis does notcompare to the digit 4 transmitted, these two correctingpulses will also run the modulo 10 summing device successively throughthe value 43 until it reaches the value 44 to exhibit the value 4 whichcompares with the magm'tude check digit.

Again, let it be assumed that by random error, the code 0110 is sent as0111. In this case the sum of the bits has been changed from even toodd. The four digit location code reports an error in the secondplaceand the modulo ten device reports a sum of 45 or a value 5 instead ofthe va1ue4 carried by the magnitude code.

In this case nine correction pulses will be transmitted to run thesecond. place register from the value 0111 successively through thevalues 1000, 1001, 0000, 0001, 0010,0011, 0100, 0101 until it reachesthe value 0110, the modulo 10 summing device advancing simultaneouslyfrom the value 45, through the values 46, 47, 48, 49, 50, 51, 52, 53until it reaches the Value 54.

By thus using a summing network to derive a parity pulse, that is, todifferentiate between an even and an odd sum of the number of bitstransmitted, it will be seen that of the single errors which stillproduce a legitimate code may be detected and corrected.

Another feature of the invention then is a parity bit generating circuitinto which the bits of a' code are entered and which in response theretowill produce an output bit when and only when the sum of the bits of thecode is odd.

While this device is shown as ameans;

7. MEANS FOR CHECKING THE IDENTITY OF ONE DECIMAL DIGIT AGAINST THEIDENTITY OF ANOTHER DECIMAL DIGIT, EACH SAID DIGIT BEING EXPRESSED INTHE 1, 2, 4 AND 8 BIT BINARY CODE, CONSISTING OF A BIT STORE FOR EACH OFSAID BINARY DIGITS OF EACH OF SAID DECIMAL DIGITS AND EACH SAID STOREHAVING A BIT OUTPUT AND A NO BIT OUTPUT, A MISMATCH NETWORK COMPRISING ATREE CIRCUIT HAVING AS A FIRST RANK THEREOF A PLURALITY OF AND CIRCUITSEACH CONNECTED TO A BIT OUTPUT FROM A STORE FOR ONE OF SAID BINARYDIGITS OF ONE OF SAID DECIMAL DIGITS AND A NO BIT OUTPUT FROM A STOREFOR A CORRESPONDINGLY VALUED BINARY DIGIT OF THE OTHER OF SAID DECIMALDIGITS, AN OUTPUT FOR EACH OF SAID AND CIRCUITS, SAID TREE CIRCUITHAVING AS A SECOND RANK THEREOF A PLURALITY OF OR CIRCUIT CONNECTED TOSAID OUTPUTS FROM SAID FIRST RANK AND CIRCUITS, AND EACH SAID SECONDRANK OR CIRCUITS HAVING AN OUTPUT, SAID TREE CIRCUIT HAVING AS A THIRDRANK THEREOF AN OR CIRCUIT CONNECTED TO SAID OUTPUTS OF SAID SECOND RANKOR CIRCUITS AND HAVING AN OUTPUT CONSTITUTING AN OUTPUT FOR SAIDMISMATCH NETWORK, A COMPLETE MATCH NETWORK COMPRISING A TREE CIRCUITHAVING AS A FIRST RANK THEREOF A PLURALITY OF AND CIRCUITS EACHCONNECTED TO A BIT OUTPUT OR A NO BIT OUTPUT FROM A STORE FOR ONE OFSAID BINARY DIGITS OF ONE OF SAID DECIMAL DIGITS AND A BIT OUTPUT OR ANO BIT OUTPUT RESPECTIVELY FROM A STORE FOR A CORRESPONDINGLY VALUEDBINARY DIGIT OF THE OTHER OF SAID DECIMAL DIGITS, AN OUTPUT FOR EACH OFSAID AND CIRCUITS, SAID TREE CIRCUIT HAVING AS A SECOND RANK THEREOF APLURALITY OF OR CIRCUITS EACH HAVING AN INPUT CONNECTED TO THE SAIDOUTPUTS OF SAID AND CIRCUITS FROM THE BIT STORES FOR EACH SAID BINARYDIGIT, AN OUTPUT FOR EACH SAID SECOND RANK OR CIRCUIT, SAID TREE CIRCUITHAVING AS A THIRD RANK THEREOF AN AND CIRCUIT HAVING INPUTS CONNECTED TOSAID OUTPUTS OF SAID SECOND RANK OR CIRCUITS AND HAVING AN OUTPUTCONSTITUTING AN OUTPUT FOR SAID COMPLETE MATCH NETWORK, A BISTABLEFLIP-FLOP HAVING A SATISFACTION SIGNAL OUTPUT, SAID FLIP-FLOP BEINGRESPONSIVE TO SAID MISMATCH NETWORK OUTPUT TO RENDER SAID SATISFACTIONSIGNAL OUTPUT DISABLED AND BEING FURTHER RESPONSIVE TO SAID COMPLETEMATCH NETWORK OUTPUT TO ENABLE SAID SATISFACTION SIGNAL OUTPUT.